1. Field of the Invention
The present invention relates to scan design for test (DFT) and, in particular, to circuitry and methods for handling high impedance conditions in integrated circuits when implementing scan DFT.
2. Discussion of the Related Art
"Testability" is an integrated circuit device design characteristic that influences various costs associated with testing the device. Usually, testability allows for determination of the status of a device, quick isolation of faults within the device, and cost-effective development of the tests themselves to determine device status.
"Design for Test" (DFT) techniques are design efforts specifically employed to ensure that a device is testable.
Two important attributes related to device testability are "controllability" and "observability." "Controllabilty" is the ability to establish a specific signal value at each node in a circuit by setting values on the circuit's inputs. "Observability" is the ability to determine the signal value at a node in a circuit by controlling the circuit's inputs and observing its outputs.
One of the most popular DFT techniques is referred to as scan design since it utilizes scan registers. A scan register is a register with both shift and parallel-load capability. The storage cells in a scan register are used as test control and/or observation points.
FIG. 1 shows a conventional scan storage cell (SSC) register chain. When TE=0 (normal mode), data are loaded into the individual scan storage cell registers 10 in parallel from associated data input lines D based upon clock signal CK. When TE=1 (test mode), data are loaded serially into the scan chain from a test line Si based upon clock signal CK. Thus, a scan register shifts test data when TE=1 and loads normal data in parallel when TE=0. Loading test data into a scan register chain when TE=1 is referred to as a scan-in operation. Reading data out of a scan register chain is referred to as a scan-out operation.
One problem associated with scan DFT is that it limits circuit designers to a very restrictive design style to the exclusion of other design practices, styles and techniques. One such restriction is a strict prohibition on the use of high impedance busses in the circuit.
However, for a variety of reasons, it is strategically desirable for integrated circuit designers to have the capability to include high impedance conditions on their devices, since it is an important design tool that is extremely useful and is widely used. The problem arises because, when test data is being shifted into a scan chain, the situation could arise in which multiple drivers 14 are attempting to drive a bus 16, as shown in FIG. 1, with clear undesirable consequences.
Therefore, it would be desirable to have available a scan design for test technique that enables the use of high impedance busses in the circuit design.